In recent years, near-data processing has been proposed in which, in an information processing device, an arithmetic circuit is provided near data to perform an arithmetic operation instead of moving data from a storage to a central processing unit (CPU) to perform an arithmetic operation.
FIG. 1A illustrates an example of an arithmetic operation in a CPU, and FIG. 1B illustrates an example of near-data processing. In a case in which a CPU 101 performs an arithmetic operation, the CPU 101 reads data from a storage 102, and performs an arithmetic operation by using the read data, as illustrated in FIG. 1A. As the storage 102, a storage such as a hard disk drive (HDD) or an SSD is used. The SSD is a storage using a semiconductor memory.
In contrast, in near-data processing, an arithmetic function moves from the CPU 101 to the storage 102, as illustrated in FIG. 1B. In this case, the CPU 101 outputs an arithmetic instruction to the storage 102, and an arithmetic circuit provided in the storage 102 performs an arithmetic operation on data.
In the near-data processing above, a cost of data movement is reduced, and high-performance power-saving arithmetic processing can be expected. Therefore, the study have become active such that a workshop dedicated to near-data processing is held, for example.
FIG. 2 illustrates an exemplary configuration of a conventional SSD that performs near-data processing (see, for example, Non-Patent Document 1). An SSD 201 of FIG. 2 includes a flash memory controller 211, and a flash memory 212-1 to a flash memory 212-4. As the flash memory 212-1 to the flash memory 212-4, a NAND flash memory that is a non-volatile memory is used, for example.
The flash memory controller 211 includes a host interface circuit (a host IF circuit) 221, a dynamic random access memory (DRAM) 222, and a processor 223. The flash memory controller 211 further includes a flash memory interface circuit (a flash memory IF circuit) 224-1 and a flash memory IF circuit 224-2. The flash memory IF circuit 224-1 is connected to the flash memory 212-1 and the flash memory 212-2, and the flash memory IF circuit 224-2 is connected to the flash memory 212-3 and the flash memory 212-4.
Hereinafter, any of the flash memory 212-1 to the flash memory 212-4 may be referred to as a flash memory 212. In addition, any of the flash memory IF circuit 224-1 and the flash memory IF circuit 224-2 may be referred to as a flash memory IF circuit 224. Each of the flash memories 212 is referred to as a chip, and a transmission line between the flash memory IF circuit 224 and the flash memory 212 is referred to as a channel. Accordingly, the number of chips in the SSD 201 indicates the number of flash memories 212, and the number of channels indicates the number of flash memory IF circuits 224.
An erasure unit of data in each of the flash memories 212 is referred to as a block, and a reading/writing unit of data is referred to as a page. The size of one block is, for example, several megabytes, and the size of one page is, for example, several kilobytes to more than ten kilobytes.
The flash memory IF circuit 224-1 performs error correction on data read from the flash memory 212-1 and the flash memory 212-2. The flash memory IF circuit 224-2 performs error correction on data read from the flash memory 212-3 and the flash memory 212-4.
The processor 223 levels the number of times of rewriting by performing wear leveling for exchanging a block for which the number of times of rewriting is large and a block for which the number of times of rewriting is small. In addition, the processor 223 performs garbage collection for releasing an unneeded page in a block, by using the DRAM 222.
In general, physical information, such as the number of chips, the number of channels, the size of a block, or the size of a page, of the SSD 201 is hidden from a host device such as a CPU.
Upon receipt of an arithmetic instruction from a host device (not illustrated), the host IF circuit 221 outputs the received arithmetic instruction to the processor 223. The processor 223 reads data from the flash memory 212, stores the data in the DRAM 222, and performs an arithmetic operation by using the data. The processor 223 stores an arithmetic result in a main storage (not illustrated) via the host IF circuit 221.
A configuration in which data search is performed within a flash memory device is also known (see, for example, Patent Document 1).    Patent Document 1: Japanese Laid-open Patent Publication No. 2003-203486    Non-Patent Document 1: Jaeyoung Do et al., “Query Processing on Smart SSDs: Opportunities and Challenges,” SIGMOD'13, pages 1221-1230, 2013.